Area - Time - Power and Design effort: the basic tradeoffs in Application Specific Systems

Using symbolic feasibility tests during design space exploration of heterogeneous multi-processor systems p. 9 Expression synthesis in process networks generated by LAURA p. 15 Artificial deadlock detection in process networks for ECLIPSE p. 22 Hardware/software interface for multi-dimensional processor arrays p. 28 Casablanca II : implementation of a real-time RISC core for embedded systems p. 36 Behavioral specification of control interface for signal processing applications p. 43 Speedups from partitioning critical software parts to coarse-grain reconfigurable hardware p. 50 A SW/configware codesign methodology for control dominated applications p. 56 Towards a framework for system-level design of multiprocessor SoC platforms for media processing p. 65 Communication-centric SoC design for nanoscale domain p. 73 Using TLM for exploring bus-based SoC communication architectures p. 79 Exploring design space of VLIW architectures p. 86 The midlifekicker microarchitecture evaluation metric p. 92 Design of a hardware accelerator for density based clustering applications p. 101 Complex fixed-point matrix inversion using transport triggered architecture p. 107 A parallel automaton string matching with pre-hashing and root-indexing techniques for content filtering coprocessor p. 113 Eliminating sorting in IP lookup devices using partitioned table p. 119 Generating efficient custom FPGA soft-cores for control-dominated applications p. 127 Multiply-accumulate architecture for a special class of optimal extension fields p. 134 Automated instruction-set extension of embedded processors with application to MPEG-4 video encoding p. 140 Instruction set architecture enhancements for video processing p. 146 Instruction set customization of application specific processors for network processing : a case study p. 154 Alleviating the data memory bandwidth bottleneck in coarse-grained reconfigurable arrays p. 161 Architectural support for accelerating congestion control applications in network processors p. 169 Power breakdown analysis for a heterogeneous NoC platform running a video application p. 179 A low-power processor architecture optimized for wireless devices p. 185 CASPER : an integrated energy-driven approach for task graph scheduling on distributed embedded systems p. 191 Via-aware global routing for good VLSI manufacturability and high yield p. 198 Virtual hierarchical design representations for distributed optimization of multi-million gate designs p. 204 Zippy-a coarse-grained reconfigurable array with support for hardware virtualization p. 213 An image processor for digital film p. 219 On estimations for compiling software to FPGA-based systems p. 225